2.6. Register tutorial

Let’s describe some register

A register is a combination of flip-flops storing configurations, flags, or triggers. A particular value in a register is called a field, and a register is the concatenation of several fields.

A common file format for exchange of information between digital and software teams is needed. Wavedrom made a proposal by generating an image from a textual representation.

In this section we present the implementation of the Wavedrom proposal. Each field is described by the following information:

  • a name

  • the number of bits of this field

  • an attribute giving extra information to it

  • a type

And a register is an ordered array of fields as represented below.

jsonml yaml toml

set the content of the file to

{reg: [
    {bits: 7,  name: 0x37, attr: ['OPIVI']},
    {bits: 5,  name: 'vd', type: 2},
    {bits: 3,  name: 3},
    {bits: 5,  name: 'simm5', type: 5},
    {bits: 5,  name: 'vs2', type: 2},
    {bits: 1,  name: 'vm'},
    {bits: 6,  name: 'funct6'},
]}

then generate an image with undulate

undulate -f svg -r -i step_1_reg.json -o step_1_reg.svg
_images/step_1_reg.json.svg

set the content of the file to

reg:
    - bits: 7
      name: 0x37
      attr: ['OPIVI']
    - bits: 5
      name: 'vd'
      type: 2
    - bits: 3
      name: 3
    - bits: 5
      name: 'simm5'
      type: 5
    - bits: 5
      name: 'vs2'
      type: 2
    - bits: 1
      name: 'vm'
    - bits: 6
      name: 'funct6'

then generate an image with undulate

undulate -f svg -r -i step_1_reg.yaml -o step_1_reg.svg
_images/step_1_reg.yaml.svg

set the content of the file to

[[reg]]
name = 0x37
bits = 7
attr = ['OPIVI']

[[reg]]
name = 'vd'
bits = 5
type = 2

[[reg]]
name = 3
bits = 3

[[reg]]
name = 'simm5'
bits = 5
type = 5

[[reg]]
name = 'vs2'
bits = 5
type = 2

[[reg]]
name = 'vm'
bits = 1

[[reg]]
name = 'funct6'
bits = 6

then generate an image with undulate

undulate -f svg -r -i step_1_reg.toml -o step_1_reg.svg
_images/step_1_reg.toml.svg

Note

Note that a name set to a number is converted into binary to zero padded if necessary to fit the size of a bus.

However, the use of number as a name is only useful to illustrate a specific configuration or state.

Note

For the coloration of a specific field, it is defined by type. The number of type and the color used is identical to the data representation for a signal (signal.wave = “=23456789”).

Tip

If you desire to remove the dashed lines in the background, add a config section at the end like as underneath. Note this is also true for previous section of the tutorial.

jsonml yaml toml
config: {
  no_ticks: true
}

config:
  no_ticks: true

config.no_ticks = true

Let’s suppose in the register, some bits are unused for the sake of field alignment to ease software writing.

Either one can precise the position of each field with regpos, or only the position of the field following the unused section.

In the example below, we desired to skip the bit 7 to align “vd” on the range [12:8], the field “nf” on the range [34:32].

jsonml yaml toml

set the content of the file to

{control:[
    {bits: 7,  name: 0x07, attr: [
    'VLxU,VLE zero-extended',
    'VLxU,VLE zero-extended, fault-only-first',
    'VLxU sign-extended',
    'VLxU sign-extended, fault-only-first',
    ]},
    {bits: 5,  name: 'vd', attr: 'destination of load', type: 5, regpos:8},
    {bits: 3,  name: 'width'},
    {bits: 5,  name: 'rs1', attr: 'base address', type: 4},
    {bits: 5,  name: 'lumop', attr: [0, 16, 0, 16], type: 3},
    {bits: 1,  name: 'vm'},
    {bits: 3,  name: 'mop', attr: [0, 0, 4, 4]},
    {bits: 3,  name: 'nf', regpos: 32},
],
config: {
    no_ticks: true
}}

then generate an image with undulate

undulate -f svg -r -i step_2_reg.json -o step_2_reg.svg
_images/step_2_reg.json.svg

set the content of the file to

control:
    - bits: 7
      name: 0x07
      attr:
      - 'VLxU,VLE zero-extended'
      - 'VLxU,VLE zero-extended, fault-only-first'
      - 'VLxU sign-extended'
      - 'VLxU sign-extended, fault-only-first'
    - bits: 5
      name: 'vd'
      attr: 'destination of load'
      type: 5
      regpos: 8
    - bits: 3
      name: 'width'
    - bits: 5
      name: 'rs1'
      attr: 'base address'
      type: 4
    - bits: 5
      name: 'lumop'
      attr: [0, 16, 0, 16]
      type: 3
    - bits: 1
      name: 'vm'
    - bits: 3
      name: 'mop'
      attr: [0, 0, 4, 4]
    - bits: 3
      name: 'nf'
      regpos: 32

config:
  no_ticks: true

then generate an image with undulate

undulate -f svg -r -i step_2_reg.yaml -o step_2_reg.svg
_images/step_2_reg.yaml.svg

set the content of the file to

[[control]]
bits = 7
name = 0x07
attr = [
    'VLxU,VLE zero-extended',
    'VLxU,VLE zero-extended, fault-only-first',
    'VLxU sign-extended',
    'VLxU sign-extended, fault-only-first'
]

[[control]]
bits = 5
name = 'vd'
attr = 'destination of load'
type = 5
regpos = 8

[[control]]
bits = 3
name = 'width'

[[control]]
bits = 5
name = 'rs1'
attr = 'base address'
type = 4

[[control]]
bits = 5
name = 'lumop'
attr = [0, 16, 0, 16]
type = 3

[[control]]
bits = 1
name = 'vm'

[[control]]
bits = 3
name = 'mop'
attr = [0, 0, 4, 4]

[[control]]
bits = 3
name = 'nf'
regpos = 32

config.no_ticks = true

then generate an image with undulate

undulate -f svg -r -i step_2_reg.toml -o step_2_reg.svg
_images/step_2_reg.toml.svg